The present invention relates to a nonvolatile semiconductor memory device and a manufacturing technology thereof, and particularly to a technology effective for application to a nonvolatile semiconductor memory device suitable for high integration and a manufacturing method thereof.
A nonvolatile semiconductor memory device capable of electrically writing or programming data therein and erasing the same therefrom is capable of rewriting data in a state of being installed onto a wiring board, for example. Since the nonvolatile semiconductor memory device is easy to use, it has widely been used for various products each of which needs a memory.
In particular, an electrically batch or collectively erase type EEPROM (Electric Erasable Programmable Read Only Memory: hereinafter called a xe2x80x9cflash memoryxe2x80x9d) has the function of collectively electrically erasing data lying in a predetermined range (all the memory cells or a predetermined memory cell group in the memory array). Further, since the flash memory has a one-transistor laminated or stacked gate structure, the downsizing of each cell has been a goal, and expectations are also high for its high integration.
In the one-transistor laminated gate structure, one memory basically comprises one two-layer gate MISFET (Metal Insulator Semiconductor Field Effect Transistor). The two-layer gate MISFET is formed by providing a floating gate electrode on a semiconductor substrate with a tunnel insulating film interposed therebetween and further laminating or stacking a control gate electrode thereon with an interlayer film interposed therebetween. Injecting electrons into the floating gate electrode and extracting the electrons from the floating gate electrode carries out the storage of data.
As one model of this type of nonvolatile semiconductor memory device, there has been known a parallel type flash memory wherein memory cells lying in respective columns or sequences of a flash memory array are connected in parallel. This has been disclosed in, for example, U.S. Pat. No. 5,793,678 corresponding to Japanese Application laid-open No. Hei 8(1996)-279566. This type of memory device is known as an AND type flash memory.
The present inventors have discussed the layout of the AND type flash memory with a view toward achieving high integration thereof. A technology discussed by the present inventors will be explained below with reference to FIG. 48.
A cell layout of the AND type flash memory discussed by the present inventors is shown in FIG. 48.
Trench type isolators SGI known in an insulation separating method generally called xe2x80x9cSTI (Shallow Trench Isolationxe2x80x9d, for example, are formed on a main surface of a semiconductor substrate 1. An insulating film is embedded into plane band-shaped trenches dug therein along a gate-width direction, so as to electrically separate between memory cells disposed along the extending direction (gate-length direction) of each word line W, whereby the isolators SGI are formed. A memory cell block MCB comprising a plurality of the memory cells is disposed in each of active regions electrically isolated by the isolators SGI.
In the memory cell block MCB, a source region of each memory cell shares the use of a local source line SS based on a buried diffusion layer wiring and is connected to one of source/drain regions of each selection MOS (not shown) connected to a common source line. Further, the drain region of each memory cell has a structure wherein it is commonly used by a sub bit line SB based on a buried diffusion layer wiring and is connected to one of source/drain regions of each MOS (not shown) connected to its corresponding main bit line. Namely, it takes a structure wherein the memory cells are connected in parallel with the local source line SS or the sub bit line SB.
Gate electrodes of individual memory cells respectively comprise floating gate electrodes (each indicated by shaded hatching in the drawing) each comprising a lower conductive or conductor film FG and an upper conductive or conductor film FL, and control gate electrodes SG formed on their floating gate electrodes with an interlayer film interposed therebetween. The control gate electrode SG acts as the word line W for each memory cell. The control gate electrodes extend in the direction orthogonal to the local source line SS or the sub bit line SB and are shared between different memory cell blocks MCBs. Assuming that a minimum processing size determined by a design rule is given as F, the word lines W are disposed side by side in parallel in plural form along a gate-length direction so that the pitch between the adjacent word lines becomes 2F. The memory cells MCs are disposed side by side in parallel in plural form along a gate-width direction so that a bit line-to-bit line pitch becomes 4F.
The scale-down of the area of each memory cell is essential for the implementation of a further cost reduction of a flash memory and high performance thereof. As a result of discussions by the present inventors, it has been considered that the narrowing of each pitch in a word-line extending direction or a bit-line extending direction (in the direction orthogonal to each word line) is effective for the downsizing of a memory cell area when the minimum processing size determined by the design rule is constant, particularly, the downsizing of a pitch extending along the bit-line extending direction due to the scale-down of the area of the upper conductor film for each floating gate electrode is effective therefor. However, it has been found that a problem arises in that the scale-down of the memory cell area by the above-described method causes a reduction in coupling ratio which is an important factor in determining the performance of operation of the flash memory.
The coupling ratio is represented by a capacitance (hereinafter represented as xe2x80x9cC1xe2x80x9d) between the semiconductor substrate and the floating gate electrode, and a capacitance (hereinafter represented as xe2x80x9cC2xe2x80x9d) between the control gate electrode and the floating gate electrode. The coupling ratio is defined by the following equation (1):
C2/(C1+C2)xe2x80x83xe2x80x83(1)
When the coupling ratio is lowered, a voltage applied to the floating gate electrode is reduced when a constant voltage is applied to the control gate electrode. Therefore, the time required to perform each of write and erase operations becomes slow. As a measure against it, there is a need to increase an operating voltage applied to the control gate electrode for the purpose of the attainment of a desired operating speed. However, an increase in operating voltage is hard to be considered as desired means from the viewpoint of the reliability of each memory cell, a request of a voltage reduction to a flash memory grown in capacity, etc.
An object of the present invention is to provide a technology capable of implementing high integration of a nonvolatile semiconductor memory device having a plurality of flash memory cells connected in parallel without causing a decrease in operating speed thereof.
The above, other objects, and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
According to a parallel type nonvolatile semiconductor memory device of the present invention, each of nonvolatile memory cells includes a lower conductor film for a floating gate electrode, which is provided on a channel region between source/drain regions with a first insulating film interposed therebetween, an upper conductor film for the floating gate electrode, which is electrically connected to the lower conductor film and is formed so as to extend on the source/drain regions from the lower conductor film with a second insulating film placed on the source/drain regions being interposed therebetween, and a conductor film for a control gate electrode, which is provided on the upper conductor film with a third insulating film interposed therebetween and serves as each word line. Widths taken along a gate-width direction, of the lower conductor film placed on the channel region and the word line are relatively thinner than those taken along the gate-width direction, of the upper conductor film placed on the second insulating film and the word line.
In the present invention as well, the widths taken along the gate-width direction, of the lower conductor film placed on the channel region and the word line are thinner than a minimum processing size determined by a design rule.
Further, in the present invention, the widths taken along the gate-width direction, of the upper conductor film placed on the second insulating film and the word line are thicker than a minimum processing size determined by a design rule.
According to a parallel type nonvolatile semiconductor memory device of the present invention as well, each of nonvolatile memory cells includes a lower conductor film for a floating gate electrode, which is provided on a channel region between source/drain regions with a first insulating film interposed therebetween, an upper conductor film for the floating gate electrode, which is electrically connected to the lower conductor film and is formed so as to extend on the source/drain regions from the lower conductor film with a second insulating film placed on the source/drain regions being interposed therebetween, and a conductor film for a control gate electrode, which is provided on the upper conductor film with a third insulating film interposed therebetween and serves as each word line.
In a central portion of a memory array, at least one first memory cell is disposed in which widths taken along a gate-width direction, of the lower conductor film placed on the channel region and the word line are relatively thinner than those taken along the gate-width direction, of the upper conductor film placed on the second insulating film and the word line. In a peripheral portion of the memory array, at least one second memory cell is disposed in which widths taken along the gate-width direction, of the lower conductor film placed on the channel region and the word line are identical to those taken along the gate-width direction, of the upper conductor film placed on the second insulating film and the word line.
According to the above-described means, even if the pitch between adjacent bit lines is narrowed to scale down or reduce a unit cell area, the areas opposed to each other between a lower conductor film for each floating gate electrode and a semiconductor substrate are reduced, whereas the areas opposed to each other between an upper conductor film for the floating gate electrode and a control gate electrode are restrained from decreasing. As a result, a reduction in coupling ratio between the control gate electrode and the floating gate electrode can be restrained from occurring.
According to the above-described means as well, at least one first memory cell capable of correcting or compensating for a reduction in coupling ratio is disposed in a central portion of a memory array, in which the thinning of a second insulating film is apt to occur. Thus it is possible to reduce or lessen variations in coupling ratio in each memory mat.
Incidentally, the technology of the present invention, of correcting the variations in coupling ratio can be applied even to a serial type nonvolatile semiconductor memory device like a NAND type as will be apparent from the description of embodiments to be described later.